Semiconductor device

ABSTRACT

A semiconductor device able to improve data retaining characteristics and decrease power consumption, further able to realize more unrestricted system without increasing excessive circuits, and having the following: an ALPG receiving a start signal and a mode selection signal to generate commands and addresses with respect to a DRAM circuit with the predetermined patterns in accordance with modes, and outputting an ending signal when ending a pattern generating processing in each of modes; an ECC circuit receiving a start signal and a mode selection signal indicating a parity generation mode to generate a parity based on data read from the DRAM circuit, receiving the start signal and a mode selection signal indicating an error correction mode to perform an error correction with respect to data read from the DRAM circuit based on the parity generated in the parity generation mode and outputting data after correcting; and an interface circuit.

CROSS REFERENCES TO RERATED APPLICATIONS

The present invention contains subject matter related to Japanese PatentApplication JP 2004-081505 filed in the Japanese Patent Office on Mar.19th, 2004 and Japanese Patent Application JP 2004-173853 filed in theJapanese Patent Office on Jun. 11th, 2004, the entire contents of whichbeing incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device embedding adynamic random access memory (DRAM), in particularly, a system circuitfor improving data retaining characteristics of the DRAM.

2. Description of the Related Art

In general, data retaining characteristics of DRAMs has been decided,for example, by the poorest one of memory cells to be mounted.

The characteristics of DRAMs has been decided by a leakage currentcharacteristic caused by a crystal defect in the memory cell andobserved as a randomly defect of a single bit at a memory cell matrix.

Moreover a defective cell caused by the factors cannot prevent even ifan improvement of producing processing is performed.

Therefore, in the general DRAM, a yield has been secured by replacing acell having a poor data retaining characteristic with a redundancy cell.

However, the method has to add the redundancy cell in accordance withthe number of defect to be secured, the increasing of area due to thatbecomes disadvantage.

Further, since the number of the redundancy cells to be mountable isrestricted, the substantial improvement of a retention cycle isdifficult.

Due to this, in recent year, it is restricted to a step that a powerconsumption of a mobile application use DRAM in a standby mode isdecreased by extending a refresh cycle drastically in the standby mode.

In recent year, as a data retention controlling circuit for DRAM, asemiconductor integrated circuit device having an ECC circuit and arefresh period setting circuit had been proposed (refer to for example,Japanese Patent Unexamined Publication (Kokai) No. 2002-56671).

The ECC circuit of the semiconductor integrated circuit device isperformed with the following first and second operations; the firstoperation is that the ECC circuit is started when entering in a dataretention mode of the memory circuit, a plurality of data retained inthe memory circuit are read, and check bits for an error detecting andcorrecting are generated and recorded; and a second operation is thatthe circuit is started when returning from the data retention mode to anormal operation wherein a read or write operation is performed betweenthe other circuits, reading a plurality of data and the check bitretained in the memory circuit is read, an error bit of data iscorrected, and writing the data is written into a corresponding memorycell.

The refresh period setting circuit is setting a period used with thecheck bit in the ECC circuit and extended within the tolerance of anerror generation, and made perform refresh operation.

The semiconductor integrated circuit system disclosed in Japanese PatentUnexamined Publication (Kokai) No. 2002□56671 can be improved the dataretaining characteristics of DRAM and decreased power consumption, butit must be prepared exclusive pattern generating circuit. When designinga circuit able to generate efficient patterns, the circuit size becomelarge, and when making circuit size in small, a pattern becomesredundancy and an operating time becomes increasing, so that it iscaught in a dilemma. Then, in usual, only circuits in minimum necessaryare mounted, but the pattern becomes redundancy as mentioned above andthe operation time becomes disadvantage.

Due to the above mentioned, the semiconductor integrated circuit systemin the above document has disadvantages in following points: (1) tomount the exclusive circuit makes excessive circuits increasing; (2) forrestraining the circuit size in small, it makes increase an operatingtime.

SUMMARY OF THE INVENTION

The present invention is to provide a semiconductor device able toimprove data retaining characteristics and decrease power consumption,further able to realize more unrestricted system without increasingexcessive circuits.

According to a first aspect of the present invention, there is provideda semiconductor device having a memory circuit including a dynamicmemory cell and performing refresh operations for retaining data of thememory circuit in a standby mode, wherein it has the following: a systemblock for outputting a start signal and a mode selection signalindicating a parity generation mode before being in the standby mode,receiving an end signal after the predetermined time to be in thestandby mode and perform a refresh operation with respect to the memorycircuit, then outputting the start signal and a mode selection signalindicating an error correction mode, and receiving the end signal afterthe predetermined time to be in a normal mode; a pattern generatingcircuit for receiving the start signal and the mode selection signalindicating the parity generation mode or the start signal and the modeselection signal indicating the error correction mode to generatecommands and addresses with respect to the memory circuit with thepredetermined pattern corresponding to a mode, and outputting the endsignal when a patter generating operation finishes in the respectivemodes; an error correcting circuit for receiving the start signal andthe mode selection signal indicating the parity generation mode togenerate a parity based on data read from the memory circuit, receivingthe start signal and the mode selection signal indicating the errorcorrection mode to perform an error correcting operation based on theparity generated with respect to data read from the memory circuit inthe parity generation mode, and outputting data after error correcting;and an interface circuit for inputting the start signal and the modeselection signal indicating the parity generation mode or the startsignal and the mode selection signal indicating the error correctionmode by the system block to the pattern generation circuit and the errorcorrection circuit, supplying commands and addresses by the patterngenerating circuit to the memory circuit, inputting data read from thememory circuit to the error correcting circuit, and outputting dataafter error correction mode processing by the error correction circuitto the memory circuit.

Preferably, the memory circuit, the system block, the pattern generatingcircuit, the error correcting circuit and the interface circuit areintegrated in a single chip.

Preferably, the pattern generating circuit is formed by a BIST (Built InSelf Test) circuit.

Preferably, the pattern generating circuit has a program retentionmemory inside, and receives the start signal to generate a patternprovided according to a program of the program retention memory.

Preferably, the memory circuit allocates a real data area and a parityarea to different areas in a recording area.

Preferably, the memory circuit is divided into a plurality of blocks,and the parity data is memorized in a block different from an area wherea corresponding real data is recoded.

According to the present invention, for example, first, for performing aparity generation in the parity generation mode, the system blockoutputs the mode selection signal and the start signal passing thoughthe interface circuit to the pattern generating circuit and the errorcorrecting circuit.

The pattern generating circuit that received the mode selection signaland the start signal, reads data from the memory circuit and inputs thesame to the error correcting circuit to generate the parity, generates aread command and address with the predetermined pattern and outputs thesame to the interface circuit.

The command and address are supplied selectivity by the interfacecircuit to the memory circuit.

Due to this, the real data and parity data are read from the memorycircuit. The data of the memory circuit is input selectivity by theinterface circuit to the error correcting circuit.

The error correcting circuit receives the start signal and the selectionsignal indicating the parity generation mode via the interface circuitby the system block. In the parity generation mode of the ECC operationmode in standby state, the parity bit is generated based on data whichis read from the memory circuit and input passing though the interfacecircuit. The parity data is stored for using in the error correctingprocessing in every standby mode of the error correction mode.

Then, when the predetermined time elapses to end the parity generationmode, the pattern generating circuit outputs an end signal via theinterface circuit to the system block.

The system block received the end signal is in standby mode that is thestate able to retain data for a long time.

The system block performs a standby refresh for data retention withrespect to the memory circuit.

Next, in order to perform the error correction in the error correctionmode, the system block outputs the mode selection signal and the startsignal passing though the interface circuit to the pattern generatingcircuit and the error correcting circuit.

The pattern generating circuit, in periods introducing to the standbymode and resetting from the standby mode, receives the start signal andthe mode selection signal indicating the error correction mode via theinterface circuit by the system block. The data read from the memorycircuit is made to input to the error correcting circuit and perform theerror correction of the defective (error) bit. Then, the real data aftercorrecting or free from correcting and the parity bit data are read fromthe error correcting circuit, a reading command and address aregenerated with the predetermined pattern and output to the interfacecircuit for writing with respect to the memory circuit.

The command and address are supplied selectivity by the interfacecircuit to the memory circuit.

Due to this, the real data and the parity data are read from the memorycircuit. Then, data of the memory circuit is input selectivity by theinterface circuit to the error correcting circuit.

The error correcting circuit receives the start signal and the selectionsignal indicating the error correction mode via the interface circuit bythe system block. In the error correction mode of the ECC operation modein the standby state, the data read from the memory circuit is inputpassing though the interface circuit, and the error correction isperformed with respect to defective data based on the parity generatedin the parity generation mode.

The error correcting circuit outputs data after error correcting orunnecessary to error correcting and the parity bit data to the interfacecircuit. Due to this, the data corrected with error is written back intothe memory circuit.

Then, when the predetermined operation finishes and the error correctionmode ends, the pattern generating circuit outputs the end signal via theinterface circuit to the system block.

The above processing is performed with respect to the entire data.

The system block received the end signal is in a normal mode that is anormal data retention mode.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and features of the present invention will bedescribed in more detail with reference to the accompanying drawings, inwhich:

FIG. 1 is a system configuration view showing a semiconductor device ofan embodiment;

FIG. 2 is a view showing an allocating example of a data area and aparity area of DRAM according to the present embodiment;

FIG. 3 is a view for explaining a method making two macros as a set formemorizing a real data and a parity data;

FIG. 4 is a view showing a corresponding relationship of a data addressand a parity address in a bank 11-0 according to the present embodiment;

FIG. 5 is a view showing a corresponding relationship of a data addressand a parity address in a bank 11-1 according to the present embodiment;

FIG. 6 is a view showing a start position and an end position ofaddresses in the banks 11-1 to 11-3 according to the present embodiment;

FIG. 7 is a view for explaining an effect by applied with a DRAM circuitaccording to the present embodiment;

FIG. 8 is a block view showing an example of a concrete configuration ofan ALPG as a DRAM pattern generating circuit according to the presentembodiment;

FIG. 9 is a view for explaining a write-back control of data when errorcorrecting;

FIG. 10 is a function block view showing a concrete configuration of atest circuit according to the present embodiment;

FIG. 11 is a view for explaining a controlling operation in an ECCoperation mode of a system block according to the present embodiment;

FIG. 12 is a timing chart in a parity generation mode when starting aparity generating page cycle;

FIG. 13 is a timing chart in the parity generation mode when ending theparity generating page cycle;

FIG. 14 is a timing chart in an error correction mode when staring aerror correcting page cycle; and

FIG. 15 is a timing chart in the error correction mode when ending theerror correcting page cycle.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Next, preferred embodiments of the present invention will be explainedwith reference to the drawings.

FIG. 1 is a system configuration view showing an embodiment of asemiconductor device of an embodiment.

A semiconductor device 10 according to the present embodiment has a DRAMcircuit 11, an algorithmic pattern generator (ALPG) 12 as a DRAM patterngenerating circuit, an ECC circuit 13 as an error correcting circuit, atest circuit 14 as an interface circuit, and system block 15, and isformed by integrating them on a single chip CP.

The semiconductor device 10 according to the present embodiment connectsa memory tester 20 outside of the chip CP to the system block 15 and canperform the predetermined test with respect to the DRAM circuit (eDRAM 0to 3) 11.

The semiconductor device 10 generates a parity bit when introducing astandby state and corrects DRAM data by the ECC circuit (an ECC decoder)when returning from the standby state, so that it can be improved a dataretaining characteristic in the standby state of the DRAM.

The semiconductor device 10 realizes a system wherein the entire systemgenerates only a start signal to be able to finish a series ofoperations of a generation of the parity data and data correction tocontrol the DRAM pattern generating circuit embedded the system ininside.

By making the pattern generating circuit as a built in self test (BIST)circuit of DRAM (in the present embodiment, the ALPG 12), the excessivecircuit mounted in the system can be decreased and the system can beoptimized.

By using the BIST circuit, since a restriction with respect to an accessto the DRAM is removed, it is possible to transfer data efficiently.

Hereinafter, the respective constructions and functions will bedescribed.

The DRAM circuit 11 has, for example, a capacity of 64 M bit, and isdivided into four banks 11-0 to 11-3 (eDRAM 0 to 3) having the capacityof 16 M bit each other.

The DRAM circuit 11 is not built into the refresh period setting circuitin the standby state, so the setting of the refresh period is performedby the system block 15. The DRAM circuit 11 is supplied with a clock bythe system block 15. When using the memory tester 20, a clock by thememory tester 20 is supplied passing thought the system block 15.

The DRAM circuit 11 performs a transfer of data (read and write) by128-bit unit in a single bank (11-0 to 11-3) with the system block 15via a bus 16.

The DRAM circuit 11 performs a transfer of the data and parity by 8-bitunit in a single bank with the test circuit 14 via a bus 17.

Further, the DRAM circuit 11 performs the transfer of commands by thesystem block 15 or commands by the ALPG 12 with the test circuit 14 viaa bus 18.

The DRAM circuit 11 stores the real data and parity bit data in therespective banks 11-0 to 11-3.

In the present embodiment, a data area and a parity area are arranged inthe respective banks 11-0 to 11-3 as shown in FIG. 2.

In an example of FIG. 2, a single bank has a memory area of 1024 row and32 column×128-bit, and is allocated with the data area of 819 row of 0to 818 and the parity area of 205 row of 819 to 1023.

In the present embodiment, as shown in FIG. 3, the banks 11-0 and 11-1and the banks 11-2 and 11-3 make the respective groups, and for example,the parity area with respect to the real data of the bank 11-0 isarranged at the bank 11-1, and the parity area with respect to the realdata of the bank 11-1 is arranged at the bank 11-0.

Due to this, the parity bit is retained by using a part of the memoryarea and secured with the parity area by swapping data when introducingstandby state.

FIG. 4 shows a corresponding relationship between the data and theparity address of the bank 11-0 (BANK 0). In the bank 11-0, a startposition is [31:0] and an end position is [95:64].

FIG. 5 shows a corresponding relationship between the data and theparity address of the bank 11-1 (BANK 1). In the bank 11-1, the startposition is [127:96] and the end position is [63:32].

Similarity, as shown in FIG. 6, in the bank 11-2 (BANK 2), the startposition is [95:64] and the end position is [31:0]. In the bank 11-3(BANK 3), the start position is [63:32] and the end position is[127:96].

By applying the DRAM circuit 11 having the above configuration, it canbe obtained with the following effects.

In the case of DRAM, when reading data, the corresponding data area hasto be activated (activate operation).

For this reason, in usual, as shown in FIG. 7A, after finishing a readoperation of the real data, the area has been performed with aninactivation (pre-charge operation), then the parity area has beenactivated and a read data has been stalled to restart the readoperation.

On the other hand, in the DRAM circuit 11 according to the presentembodiment, as shown in FIG. 7B, the real data area and the parity dataarea are separated among the macros or banks and stored the same in themacros or banks, so that the read operation of the real data and theread operation of the parity can be performed continuously and theefficient data transfer becomes possible.

The ALPG 12 as the DRAM pattern generating circuit receives a startsignal RUN and a selection signal EMS indicating the parity generationmode via the test circuit 14 by the system block 15, and reads out datafrom each of the banks 11-0 to 11-3 of the DRAM circuit 11 in the paritygeneration mode of the ECC operation mode in the standby state. Then itgenerates commands and addresses with the predetermined pattern andoutputs the same to the test circuit 14 to make it input to the ECCcircuit 13 and generate the parity. Then, when the predetermined timeelapses to end the parity generation mode, it outputs the end signal ENDvia the test circuit 14 to the system block 15.

The ALPG 12 receives the start signal RUN and the selection signal EMSELindicating the error correction mode via the test circuit 14 by thesystem block 15 after the standby mode and the refresh period elapse,reads out data from each of the banks 11-0 to 11-3 of the DRAM circuit11 and makes it input and the ECC circuit 13 perform the errorcorrection in the error correction mode of the ECC operation mode in thestandby state. Then it generates commands and addresses for writing withrespect to each of the banks 11-0 to 11-3 of the DRAM circuit 11 withthe real data and the parity data output by the ECC circuit 13 with thepredetermined pattern, and outputs the same to the test circuit 14.Then, when the predetermined time elapses to end the error correctionmode, it outputs the end signal END via the test circuit 14 to thesystem block 15.

Due to this, a series of operations in which the parity bit is generatedwhen introducing standby state and the DRAM data is corrected inreturning from standby state by the ECC circuit (ECC decoder) 13 iscontrolled by the ALPG 12 in accordance with the start signal RUN fromthe system block 15.

The ALPG 12 is a pattern generating circuit for generating the commandand data in the BIST system, so it has a permissibility generating a lotof patterns required for testing the DRAM free from restraint.

In particular, in the case of devices having an embedded DRAM or other alot of bits I/O, a test use bus interconnection able to lead to outsideof the chip CP must be limited (in the present embodiment, it is 8-bit).

Consequently, by using the ALPG 12, the efficient command pattern can begenerated without staling DRAM (or data bas).

FIG. 8 is a block view showing an example of a configuration of the ALPG12 as the DRAM pattern generating circuit according to the presentembodiment.

The ALPG 12 shown in FIG. 8 has a command storing unit 121, a storedcommand read controlling unit 122, and a generation pattern operationunit 123.

In the ALPG 12, data in the command storing unit 121 built into it isread by the stored command read controlling unit 122, and commandpatterns and address patterns are generated by the generation patternoperation unit 123 from the read command.

Due to this, by rewriting data of the command storing unit 121, it hasalso an advantage able to rewrite a command pattern easily.

The ECC circuit 13 receives the start signal RUN and the selectionsignal EMSEL indicating the parity generation mode via the test circuit14 by the system block 15, and generates parity bit data of 32-bit basedon data read from the each of banks 11-0 to 11-3 of the DRAM circuit 11and input passing though the test circuit 14 in the parity generationmode of the ECC operation mode in the standby state.

The ECC circuit 13, after the standby mode and the refresh period elapseand before returning to the normal operation, receives the start signalRUN and the selection signal EMSEL indicating the error correction modevia the test circuit 14 by the system block 15, inputs data read fromeach of the banks 11-0 to 11-3 of the DRAM circuit 11 passing throughthe test circuit 14 in the error correction mode of the ECC operationmode in the standby mode, performs the error correction with respect tothe defective data based on the parity generated in the paritygeneration mode, and outputs data after error correcting or unnecessaryto error correcting and the parity bit data to the test circuit 14.

The ECC circuit 13 transfers an error status data passing though thetest circuit 14 to the system block 15.

The test circuit 14 supplies the start signal RUN and the selectionsignal EMSEL indicating the parity generation mode or the errorcorrection mode by the system block 15 to the ALPG 12 and the ECCcircuit 13, and functions as the interface circuit for data transferringbased on the command and the address data generated by the ALPG 12between each of the banks 11-0 to 11-3 of the DRAM circuit 11 and theECC circuit 13.

The test circuit 14 supplies the error status information of the ECCcircuit 13 to the system block 15.

Note that, in the error correction mode, only when there is correctingbits, data of 128-bit is written back to the banks 11-0 to 11-3 of theDRAM circuit 11.

If unnecessary to correct, the write operation to the banks 11-0 to 11-3is controlled not to perform.

The condition is referred to a signal for the number of corrected bit ofthe ECC circuit 13, if the number of the corrected bit is not 0, thewrite-back operation is performed with respect to the banks 11-0 to11-3.

Even if there are a lot of defects to be impossible to correct or theECC circuit 13 performs the mistaken correction, referring to only thenumber of corrected bit, the write operation is performed to the banks11-0 to 11-3.

Further, the command signal is, as shown in FIG. 9, common to a firstset (group) of the banks 11-0 and 11-1 and a second set (group) of thebanks 11-2 and 11-3, even if one set has the corrected bit and anotherdoes not have the corrected bit, the write operation is performed withrespect to the both set.

The signal for the number of corrected bits is discriminated, forexample, by the test circuit 14, and the control above mentioned isperformed.

FIG. 10 is a function block view showing a concrete configuration of thetest circuit 14.

The test circuit 14 is, as shown in FIG. 10, has an address FIFO(First-In First-Out) 141, data FIFOs 142 and 143, an error status unit144, and selectors 145 to 147.

The address FIFO 141 receives signals IOR and ES by the ALPG 12, retainsthe address data by the ALPG 12, and supplies the same to each of thebanks 11-0 to 11-3 of the DRAM circuit 11.

The address FIFO 142 receives a signal 0_START by the ALPG 12, retainsdata by the ECC circuit 13, receives the signal IOR and supplies theretained data to the banks 11-0 and 11-1.

The address FIFO 143 receives the signal 0_START by the ALPG 12, retainsdata by the ECC circuit 13, receives the signal IOR and supplies theretained data to the banks 11-2 and 11-3.

The error states unit 144 receives error status information by the ECCcircuit 13 and outputs the same as a signal ECCSTS to the system block15.

The selector 145 selectively inputs read data of the bank 11-0 or bank11-1 to the ECC circuit 13 based on the selection signal by the ALPG 12.

The selector 146 selectively inputs selectively read data of the bank11-2 or bank 11-3 to the ECC circuit 13 based on the selection signal bythe ALPG 12.

The selector 147 selectively supplies selectively the command by theALPG 12 to the banks 11-0 and 11-1 or the banks 11-2 and 11-3 based onthe selection signal by the ALPG 12.

The system block 15 controls the entire system, in the ECC operationmode as shown in FIGS. 11A to 11F, outputs the mode selection signalEMSEL and the start signal RUN passing though the test circuit 14 to theALPG 12 and the ECC circuit 13.

The system block 15, first, outputs the mode selection signal EMSEL andthe start signal RUN passing though the test circuit 14 to the ALPG 12and the ECC circuit 13 in order to perform a parity generation in theparity generation mode.

The system block 15, after ending the parity generation mode, performs astandby refresh for data retention with respect to the DRAM circuit 11based on the standby signal STBY and standby clock SCLK.

The system block 15, after ending the standby refresh, outputs the modeselection signal EMSEL and the start signal RUN passing though the testcircuit 14 to the ALPG 12 and the ECC circuit 13 to make it perform anoperation of the error correction mode for correcting defective (error)bits.

The system block 15 becomes the normal mode after ending the errorcorrection mode, for example, and performs normal controls to memoryaccess passing through the bus 16.

Next, an introducing or returning sequence to standby by the aboveconfigurations will be described with reference to timing charts of FIG.12 to FIG. 15.

FIG. 12 is a timing chart in the parity generation mode at the time ofstarting a parity generating page cycle. FIG. 13 is a timing chart inthe parity generation mode at the time of ending the parity generatingpage cycle.

FIG. 14 is a timing chart in the error correction mode at the time ofstarting an error correcting page cycle. FIG. 15 is a timing chart inthe error correction mode at the time of ending the error correctingpage cycle.

Introducing to Standby

In order to perform the parity generation in the parity generation mode,the system block 15 outputs the mode selection signal EMSEL and thestart signal RUN passing though the test circuit 14 to the ALPG 12 andthe ECC circuit 13.

The ALPG 12 that received the mode selection signal EMSEL and the startsignal RUN generates a read command RD and addresses AY and TAY as shownin FIGS. 12 and 13 with the predetermined pattern, and outputs them tothe test circuit 14 in order to read data from the respective banks 11-0to 11-3 of the DRAM circuit 11 and input to the ECC circuit 13 to makeit generate parity.

The read command RD of a data side is a command for reading data of128-bit, and the data among the banks 11-0 to 11-3, the test circuit 14and the ECC circuit 13 is transferred by 8-bit, so that the command R isgenerated for dividing and transferring in 8-bit.

The generated parity bit data of 32-bit is divided into 8-bit similar toat the time of reading and transferred to the bank. The macro is writtenand divided by using a writing function mask in every 8-bit for fourtimes.

The commands and addressees are selectively supplied by the selector 147of the test circuit 14 to the banks 11-0 to 11-3 of the DRAM circuit 11.

Due to this, the real data and the parity data are read from the banks11-0 to 11-3 in 8-bit unit. The data in the banks 11-0 and 11-1 areselectively input by the selector 145 of the test circuit 14 to the ECCcircuit 13. Similarly, the data in the banks 11-2 and 11-3 areselectively input by the selector 146 of the test circuit 14 to the ECCcircuit 13.

The ECC circuit 13 receives the start signal RUN and the selectionsignal EMSEL indicating the parity generation mode via the test circuit14 by the system block 15. In the parity generation mode of the ECCoperation mode in the standby state, the parity bit of 32-bit isgenerated based on data read from each of the banks 11-0 to 11-3 of theDRAM circuit 11 and input passing though the test circuit 14. The paritydata is stored for using in the error correcting operation of the errorcorrection mode in every standby mode.

Then, when the predetermined time elapses to end the parity generationmode, the ALPG 12 outputs the end signal END via the test circuit 14 tothe system block 15.

The system block 15 received the end signal END enters in the DRAMstandby mode that is able to retain data for a long time.

The system block 15 performs the standby refresh with respect to theDRAM circuit 11 for data retention based on the standby signal STBY andthe standby clock SCLK.

Returning from Standby

Next, in order to perform the error correction in the error correctionmode, the system block 15 outputs the mode selection signal EMSEL andthe start signal RUN passing though the test circuit 14 to the ALPG 12and the ECC circuit 13.

After standby mode and refresh period, the ALPG 12 receives the startsignal RUN and the mode selection signal EMSEL indicating the errorcorrection mode via the test circuit 14 by the system block 15, readsdata from each of the banks 11-0 to 11-3 of the DRAM circuit 11, andinputs the same to the ECC circuit 13 to make it perform errorcorrection of the defective (error) bit. The real data after correctingor unnecessary to error correction are read from the ECC circuit 13, andthe read command RD, a write command W, and the addresses AY and TAY asshown in FIGS. 14 and 15 are generated with the predetermined patternand output to the test circuit 14 to make it write with respect to eachof the banks 11-0 to 11-3 of the DRAM circuit 11.

The commands and addresses are selectively supplied by the selector 147of the test circuit 14 to the banks 11-0 to 11-3 of the DRAM circuit 11.

The address of the time of writing operation is supplied passing thoughthe address FIFO 141 of the test circuit 14 to the respective banks 11-0to 11-3.

Due to this, the real data and the parity data are read from the each ofbanks 11-0 to 11-3 by 8-bit unit. The data of the banks 11-0 and 11-1are selectively input by the selector 145 of the test circuit 14 to theECC circuit 13. Similarly, the data of the banks 11-2 and 11-3 areselectively input by the selector 146 of the test circuit 14 to the ECCcircuit 13.

The ECC circuit 13 receives the start signal RUN and the selectionsignal EMSEL indicating the error correction mode via the test circuit14 by the system block 15. In the error correction mode of the ECCoperation mode in the standby mode, the data read from each of the banks11-0 to 11-3 of the DRAM circuit 11 is read passing though the testcircuit 14 to perform the error correction with respect to the defectivedata based on the parity generated in the parity generation mode.

Then, the ECC circuit 13 outputs data after correcting or unnecessary tocorrecting and parity bit data to the test circuit 14. Due to this, datacorrected errors are written back to the predetermined banks 11-0 to11-3.

The ECC circuit 13 transfers an error status passing though the testcircuit 14 to the system block 15.

Then, when the predetermined operation is finished to end the errorcorrection mode, the ALPG 12 outputs the end signal END via the testcircuit 14 to the system block 15.

The above processing is performed with respect to the entire data.

The system block 15 received the end signal END is in the normal modethat is normal data retention mode.

As mentioned above, according to the present embodiment, thesemiconductor device 10 has the following units: the system block 15 foroutputting the start signal and the mode selection signal indicating theparity generation mode before entering the standby mode, receiving theend signal after the predetermined time to perform a refresh operationwith respect to the DRAM circuit 11 in the standby mode, then outputtingthe start signal and the mode selection signal indicating the errorcorrection mode, and receiving the end signal after the predeterminedtime to enter in the normal mode; the ALPG 12 for receiving the startsignal and the mode selection signal indicating the parity generationmode and the start signal and the mode selection signal indicating theerror correction mode to generate the commands and addresses withrespect to the DRAM circuit 11 with the predetermined pattern inaccordance with the mode, and outputting the end signal when the pattergenerating operation is finished in the respective mode; the ECC circuit13 for receiving the start signal and the mode selection signalindicating the parity generation mode to generate a parity based on dataread from the DRAM circuit 11, receiving the start signal and the modeselection signal indicating the error correction mode to perform theerror correcting processing with respect to data read from the DRAMcircuit 11 based on the parity generated in the parity generation mode,and outputting data after error correcting; and the test circuit 14 forinputting the start signal and the mode selection signal indicating theparity generation mode, and the start signal and the mode selectionsignal indicating the error correction mode by system block 15 to theALPG 12 and the ECC circuit 13, supplying the commands and addresses bythe ALPG 12 to the DRAM circuit 11, inputting data read from the DRAMcircuit 11 to the ECC circuit 13, and outputting data after the errorcorrection mode processing by the ECC circuit 13 to the DRAM circuit 11.As a result, the following effects can be obtained.

It is possible to improve the data retaining characteristics in thestandby state of DRAMs.

By controlling a system by the ALPG 12 as a DRAM pattern generatingcircuit embedded inside, the system block 15 only generates the startsignal, it can be realized the system able to complicate a series ofoperations of the generation of the parity data and the data correction,subsequently, then it can be reduced a load of the system block 15controlling the entire system.

Besides, since the ALPG 12 of the patter generating circuit is the DRAMBIST (Built In Self Test) circuit, the excessive circuit mounted insystem can be reduced and the system can be optimized. By using the BISTcircuit, a restriction with respect to accesses to DRAM is removed, itis possible to transfer data efficiency.

Moreover, the ALPG 12 has a program retention use memory with internal,by supplying only the start signal, it is possible to generate theprovided patterns (command groups). When changing the provided pattern,it is possible to change easily only changing memory contents.

Further, the refresh period setting circuit in the standby state canperform a refresh operation by the outer memory controller free frombuilt-in eDRAM system. Due to this, the refresh period in the standbystate is changeable a setting to the optimized amount considered withsurroundings such as chip temperatures.

The parity bit is retained by using a part of the memory area, so thatthe parity area can be secured by swapping data at the time of standbyintroduction. And the parity area is retained in the other banks orother blocks, so that efficient data transferring is possible at thetime of transferring the real data or parity data.

Due to controlling by using the BIST circuit, by rewriting memory data,it has advantage that the real data area and parity data area can be setfree from restrict.

Due to controlling by using the BIST circuit, it is possible to improvea faultless detecting rate of the ECC system at quality test whenproducing.

As mentioned above, due to using the present invention, a DRAM refreshcycle in the standby state can be extend remarkably, the effectdecreasing power consumption due to this can be achieved parallel to theincrease of the circuit size making minimum necessary.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors in so far as they arewithin scope of the appeared claims or the equivalents thereof.

1. A semiconductor device having a memory circuit including a dynamic memory cell and performing a refresh operation for retaining data of said memory circuit in a standby mode, comprising: a system block for outputting a start signal and a mode selection signal indicating a parity generation mode before entering in the standby mode, entering in the standby mode when receiving an end signal after the predetermined time and perform the refresh operation with respect to said memory circuit, then outputting a start signal and a mode selection signal indicating an error correction mode, and entering in a normal mode when receiving the end signal after the predetermined time; a pattern generating circuit for receiving said start signal and said mode selection signal indicating said parity generation mode, and said start signal and said mode selection signal indicating said error correction mode to generate commands and addresses with respect to said memory circuit with the predetermined pattern in accordance with a mode, and outputting said end signal when the patter generating operation is finished in the each mode; an error correcting circuit for receiving said start signal and said mode selection signal indicating said parity generation mode to generate a parity based on data read from said memory circuit, receiving said start signal and said mode selection signal indicated said error correction mode to perform an error correcting operation based on a parity generated with respect to data read from said memory circuit in said parity generation mode, and outputting data after error correcting; and an interface circuit for inputting said start signal and said mode selection signal indicating said parity generation mode, and said start signal and said mode selection signal indicating said error correction mode by said system block to said pattern generating circuit and said error correction circuit, supplying the commands and addresses by said pattern generating circuit to said memory circuit, inputting data read from said memory circuit to said error correcting circuit, and outputting data after an error correction mode processing by said error correction circuit to said memory circuit.
 2. A semiconductor device as set forth in claim 1, wherein said memory circuit, said system block, said pattern generating circuit, said error correcting circuit and said interface circuit are integrated in a single chip.
 3. A semiconductor device as set forth in claim 2, wherein said pattern generating circuit comprises a built in self test (BIST) circuit.
 4. A semiconductor device as set forth in claim 3, wherein said pattern generating circuit comprises a program retention memory inside, and receives said start signal to generate a pattern provided according to a program of said program retention memory.
 5. A semiconductor device as set forth in claim 4, wherein said program retention memory is changeable with retaining content.
 6. A semiconductor device as set forth in claim 2, wherein said memory circuit allocates a real data area and a parity area to different areas in a recording area.
 7. A semiconductor device as set forth in claim 6, wherein said memory circuit is divided into a plurality of blocks and said parity data is stored in a block different from an area where a corresponding real data is recoded.
 8. A semiconductor device as set forth in claim 7, wherein said memory circuit makes two blocks as one set and stores real data at the real data area of one block and corresponding parity data at the parity area of another block.
 9. A semiconductor device as set forth in claim 2, wherein, in said error correction mode, said interface circuit, supplies data to said memory circuit to write back only when there is a correcting bit.
 10. A semiconductor device as set forth in claim 8, wherein, in said error correction mode, said interface circuit, supplies data to said memory circuit to write back only when there is a correcting bit.
 11. A semiconductor device as set forth in claim 10, wherein a command generated by said pattern generating circuit and supplied to said memory circuit passing though said interface circuit is common in each of sets, even if one set has a correcting bit and another set does not have a correcting bit, said interface circuit, writes back data with respect to all sets. 